Re: Re: [openrisc] is this a bug in or1200's except logic?

["qcpassed" <qcpassed@sina.com>]

Damjan Lampret

	Sorry now I know it's my fault.
	The instruction memory should latch the output(icpu_dat_i) on the rising edge of clock when the icpu_cycstb_o asserts.Because cpu's output signal  icpu_adr_o will change as soon as the icpu_ack_i asserts.My analysis last time was wrong,because icpu_rty_i asserts when  icpu_cycstb_o deasserts and icpu_adr_o is equal to icpu_adr_i etc.

>How did you test this? Did you use SW test case? If yes, can you send it.
>Thanks.
>
>regards,
>Damjan
>
>----- Original Message -----
>From: "qcpassed" <qcpassed@sina.com>
>To: <openrisc@opencores.org>
>Sent: Thursday, April 10, 2003 8:37 PM
>Subject: [openrisc] is this a bug in or1200's except logic?
>
>
>  I only simulate the or1200_cpu logic with modelsim.
>  I found that the exception vector's first instruction will never be
>excuted when a exception,trap or syscall happen.
>The reason is listed bellow:
>  1) first I list the related original codes
>file://-----------------in or1200_genpc.v---------------------------
> assign icpu_cycstb_o = !genpc_freeze;
>always @(posedge clk or posedge rst)
>if (rst)
>pcreg <= #1 30'd63;
>else if (spr_pc_we)
>pcreg <= #1 spr_dat_i[31:2];
>else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i &
>!genpc_refetch)
>// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
>pcreg <= #1 pc[31:2];
>file://-----------------in or1200_freeze.v--------------------------
>assign genpc_freeze = du_stall | flushpipe_r;
>always @(posedge clk or posedge rst)
>if (rst)
>flushpipe_r <= #1 1'b0;
>else if (icpu_ack_i | icpu_err_i)
>//  else if (!if_stall)
>flushpipe_r <= #1 flushpipe;
>else if (!flushpipe)
>flushpipe_r <= #1 1'b0;
>file://----------------in or1200_except.v--------------------------
>assign flushpipe = except_flushpipe | pc_we | extend_flush;
>assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
>2)my analysis
>When extend_flush deasserts,except_start also deasserts,but genpc_freeze
>still keep high untill next clock.
>So on next clock pc_reg changes to except vector's start address,pc changes
>to next instruction of the vector,
>icpu_cycstb_o assert,but at this time icpu_adr_o is equal to pc,but not
>except vector's start address.
>So the first instruction is skipped because of the bug of logic.
>
>3)The testbench file,or1200_define.v and wave.do are in attachment.
>
>
>????????????????qcpassed
>????????????????qcpassed@sina.com
>????????????????????2003-04-11
>
>
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>.

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¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡qcpassed
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¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2003-04-14

or1200_cpu_tb.tf