Re: [openrisc] is anyone reading or1200?i have some questions to talk about

["Damjan Lampret" <lampret@opencores.org>]

Qcpassed,

why don't your run some code and see in simulation how everything plays out.
It is too complicated to discuss all the different scenarios how or1200
pipeline works. If you think you have found a bug, please provide test code.
However I can assure you that chances are small as things have been very
much tested in the last year since last major changes were made to the
design.

regards,
Damjan

----- Original Message -----
From: "qcpassed" <qcpassed@sina.com>
To: <openrisc@opencores.org>
Sent: Wednesday, April 09, 2003 1:00 AM
Subject: [openrisc] is anyone reading or1200?i have some questions to talk
about


>      or1200_except.v is too difficult for me to understand.
>      when exception happens:
>     1¡ê? what will happen when the current instruction(ex_insn) is a lsu
instruction in delay slot and lsu_unstall is not    asserted?
> 2¡ê? will the result be writen back to rf when current
instruction(ex_insn)  writes rf in delay slot?
>         by the way,it seems that the result will be writen back to rf,but
the epcr will still be set to the branch instruction.Then when expection
returns the delay slot instruction will  excute again and will write rf
again.
> 3)etc.
>     I have a lot question,does anyone can give me a hand?
>
>
>
>
> ????????????????qcpassed
> ????????????????qcpassed@sina.com
> ????????????????????2003-04-09
>
>
>
>
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