Re: [openrisc] Running slower wishone interfaces

["Damjan Lampret" <lampret@opencores.org>]

Michael,

I don't know if you know, but WB clocks needs to be in phase with the main
clock.

You can also send you or1200_defines.v to the list (or to me privately what
ever you prefer) and I'll have a look.

regards,
Damjan

----- Original Message -----
From: Michael Scott <mike.scott@jennic.com>
To: <openrisc@opencores.org>
Sent: Monday, March 31, 2003 2:37 AM
Subject: [openrisc] Running slower wishone interfaces


> Hi All,
>       I've just managed to get the OpenRISC core running under Modelsim
5.6.
> However
> It only seems to work with the Risc clock & Wishbone clock running at 1:1
> I've tried changing the appropriate defines and the clmode input for 1:2
and
> 1:4 ratios
> but the instruction address doesn't appear increment correctly. Instead of
> fetching
> from 0x100, 0x104, 0x0108  it follows 0x100, 0x108, 0x110
> This looks suspiciously like a clock domain issue and a missing
synchroniser
> somewhere but
> I've checked the code & defines and it seems ok
>
> Has anybody successfully run the core under modelsim with slower
> (half/quarter speed)
> wishbone interfaces on instruction/data memories ?
>
>
> Regards,
>
> Mike Scott
>
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