Re: [openrisc] OR1200 implementation of l.sb and l.sh

[=?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>]

>BTW the simplest way to prove this is because there are four data cache RAM
>cells, one RAM cell per byte (you can replace them by single RAM instance
>with byte write enables if you ASIC memory compiler supports this).

Hi!
Now I see what you mean! I was mislead, because I thought dc_ram was a single 
32-bit ram instead of 4 8-bit rams.
Thank you for this clarification.

Best regards,

Marķa Bolado


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