Re: [openrisc] CID bits and shadow registers

[Marko Mlinar <markom@opencores.org>]

On Friday 18 October 2002 15:24, mbtirado@mundivia.es wrote:
> Thank you very much, Marko.
> I am not sure what you mean with "normal virtual memory architecture"
> Do you mean an architecture where the OS changes the base pointer of
> the page table with every context change, so we have a different page
> table for every process? Or instead processes can't use the entire
> memory virtual address but only a part?
What I had in mind is virtual memory architecture without contexts, e.g. i386.
If you don't have multiple TLB, you have to invalidate current entries and 
wait for page fault exceptions to fill them up with new numbers.

> Apart from these, I have another question that I hope it might be the
> last: żis it possible to implement CID bits (not hardwiring to zero)without
> implementing shadow registers in an OR1000 architecture? As far as I
> have read the manual, it is not clear if CID bits and shadow registers are
> unavoidably together or not.
You could do that, but if you are implementing fast context switching it is 
smart to put everything that has to be done at context switch in HW.

Marko

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