Re: [openrisc] Re: PC as GPR?

["Damjan Lampret" <lampret@opencores.org>]

> Yeah, the register window functionality would need major changes.  A
> store/load of multiple registers however is (at least from the software
> point of view) a simple addition which doesn't change the architecture
> in a significant way.  Except for making it much more icache efficient.

I personally think more from HW POV. I like the idea, just I have a bad
feeling it will interfere with HW debug. And of course even if DC can
perform multiple operations per clock cycle, it will take multiple clock
cycles to read/write multiple GPRs. I thinking we could have a list of
optional instructions that you can enable both in HW (obviously before you
"build" your HW) and in GCC with a switch. Of course this would mean that if
you want to have fast system, you would have to rebuild most of the shared
software (libraries).

I'd like to have very minimal set of instructions (integer) that allow
building of very small and simple RISCs for use in FPGAs. That's why I think
all the instructions that are only for performance optimizations, should be
optional (or at least you can kick them out when you want to compile for
small/simple RISC).

regards,
Damjan


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