Re: [openrisc] Re: PC as GPR?

["Jim Dempsey" <tapedisk@ameritech.net>]

----- Original Message ----- 
From: "Marko Mlinar" <markom@opencores.org>
To: <openrisc@opencores.org>
Sent: Wednesday, February 27, 2002 12:49 AM
Subject: Re: [openrisc] Re: PC as GPR?


> > You are using a PLD here, aren't you? Part of this discussion also
> > touched on adding floating point and other instructions. I would
> > think that a generic instruction extension capability would be in
> > order. Something like that in the NIOS processor. Or if that
> > doesn't fit in with the design then consider the Escape sequence
> > used on the 8086 and like processors. For the string instructions
> > and block operations you would incorporate the instructions in
> > logic using possibly a DMA core in conjunction with a limited
> > FIFO (to byte align the operations). QED
> I am not sure at what exaclty are you aiming at, but or1k architecture
> document defines floating point instructions and there is still a lot of
> space for special instructions. Escape sequences would just destroy
> the whole concept of simple RISC with instruction length always = 32b.
> 
RISC does not necessarily mean instruction length always = 32b.
RISC means Reduced Instruction Set Computer. i.e. fewer instructions.
The intention of RISC is less logic = faster code (or fast enough code).
Adding string instructions goes contrary to this philosophy - so too would
be adding floating point instructions. I am not recommending that these
not be added. I am simply stating that by adding these instructions you
also are migrating away from RISC.

Notice that by placing floating point instructions inside the processor
core (or along side it) means a larger core. Software emulation of
floating point would use code stored in memory. Memory is typicaly
cheaper than PLD space. So you have a cost / power / performance
and other factors to keep in mind. 

I would like to make a suggestion to design the processor to be
tuneable to meet the particular needs. For example, if someone
has a non-performance oriented requirement for floating point
that they can generate a processor core without the integrated FPU
however the FPU instruction when executed performs a trap to
code that emulates the FPU instruction. In this manner the same
object code runs in both environments. This is the same for any
other instructions that you might consider adding.

Jim
 



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