回信： [openrisc] OR1K VHDL simulation problem

[jimmy87@sunplus.com.tw]

I think you have to wait for Damjan.
He's busy with exams now.
(I use Verilog..., and never use Xilinx before)
Best regards, Jimmy





"Chen Zhang" <C_Zhang@lbl.gov> 於 2000/06/15 01:11:18 AM

請回應 給 openrisc@opencores.org

收件人：  openrisc@opencores.org
副本抄送： (副本密送： jimmy87/Sunplus)

主旨：    [openrisc] OR1K VHDL simulation problem



I tried to simulate the OR1k VHDL files with ModelSim, however, the
component ram16x1s is missing, thus the Regfile does not work properly.
Please advise how to solve this problem.


Chen Zhang