[openip] Simplex, Toshiba prep diagonal interconnect scheme [ EETimes ]

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[ http://www.eet.com/story/OEG20010604S0087 ]

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Simplex, Toshiba prep diagonal interconnect scheme
By Anthony Cataldo and Brian Fuller, EE Times
Jun 4, 2001 (10:28 AM)
URL: http://www.eetimes.com/story/OEG20010604S0087

SAN MATEO, Calif. — Claiming a semiconductor breakthrough as significant as copper interconnects, Simplex Solutions Inc. and
partner Toshiba Corp. have developed a means for designers to route on-chip wires diagonally, enabling a 20 percent average
reduction in wire length as well as improved performance and lower power consumption, the companies said.

To rally support for the novel routing scheme, dubbed the X Architecture, the two companies are forming an independent consortium
— the X Initiative — to promote the use of the so-called gridless octilinear routing scheme. Simplex plans to provide more
technical details of its Liquid Routing technology, which lies behind the X Architecture, in coming weeks, and the consortium is
to hold its first formal meeting at the Design Automation Conference later this month.

If companies can manufacture such devices reliably with high yield, the approach would achieve an engineering trifecta: higher
performance, improved real estate utilization and lower power consumption. The approach has been tried before, however, often with
poor results. The scheme, which supplements the classic "Manhattan-style" 90° routing turns, places an emphasis on mask-making
techniques, and in extreme high frequencies some unwanted effects could theoretically occur to degrade signals.

Still, Penny Herscher, chairwoman and chief executive at Simplex (Sunnyvale, Calif.), said interspersing diagonal wires with
conventional orthogonal wires is the next step beyond copper to further alleviate interconnect-delay problems that now dominate
submicron designs.

"What the industry has been trying to do is minimize interconnect delay, and the first thing was to look at the material, which is
where copper came from," Herscher said in a recent interview. "This goes after the other half of the problem."


Improvement estimates

To Simplex, that means shorter wires. By its own estimates, wire length is reduced by 20 percent on average using diagonal
interconnects. The result is a 10 percent jump in chip performance, 20 percent reduction in power consumption and 30 percent more
chips per wafer, due to the smaller size, according to the company.

To reach this level of improvement, a device can theoretically use diagonal wires throughout, though in fact, they will be used
more often in some places on a chip than in others.

"At a global level, [the wires] are mostly going in one direction on each layer. But when it's making a local decision to route,
they can go in any direction at any metal level," Herscher said.

In a five-metal-layer design, Simplex has divided the labor between the lower three metal layers and the top two. The lower layers
will remain dominantly orthogonal, for compatibility with existing cores and macros. "Then, if there's room, you would use
whatever direction would give you the shortest distance," Herscher said.

The top two layers, however, will make heavy use of diagonals to carry the signals. At the fourth metal level, the preferred
direction is southwest to northeast, while at the fifth level, it's southeast to northwest. Though designed for five layers,
Liquid Router can be used for any design above that number, Herscher said.

The idea of using diagonal interconnect is not new, but the computing power and algorithms needed to put it into practice have
been tough nuts to crack.

"People have been using diagonals inside memory cells, but it's never been used pervasively for digital designs," Herscher said.
"There wasn't the compute power to make it possible. The critical issue was being able to do the algorithms needed to do basic
diagonal routing. It took a lot of high-powered people and a lot of investment in extraction technology to do the parasitics."

Simplex set out to tackle diagonal interconnects three years ago by hiring Aki Fujimura as president and chief operating officer
and Steven Teig as chief technology officer. Both men were behind the development of algorithmic approaches to interconnect for
sea-of-gates devices while working at Tangent Systems, which was later bought by Cadence Design Systems Inc.

So far, Simplex has disclosed few details on the physical-design software that implements the X Architecture and has not said
whether it plans to offer a specific EDA tool to do the job. Herscher said Simplex plans to work with individual companies that
want to adopt the technology, starting with Toshiba, but did not provide a timetable.

Those two companies, which have worked for two years on the project, said they have completed a RISC processor design using X
Architecture. They hope to tackle additional designs next year, the pair said.


Support plan

Garnering widespread industry support — from fabrication to design — for the X Architecture is another part of Simplex's game plan
and the motive behind forming the X Initiative. Its members include Dai-Nippon Printing, Du Pont Photomask, Etec Systems, Toshiba
Machines and KLA-Tencor for mask preparation; Tensilica and Virtual Silicon Systems for developing cores and libraries; Toshiba
Corp. for fabrication; and Simplex for the physical-implementation and extraction technologies.

Simplex has licensed its technology only to Toshiba, and is not discussing its licensing plans publicly. However, the company
hopes its competitors will join the consortium. "We have been open in discussions with other EDA companies and we don't see them
as competitors on this issue," Herscher said. "We're encouraging them to join."

The most immediate impact of the X Architecture will be to help automate custom-IC design, said Gary Smith, chief EDA analyst at
Gartner Dataquest. Early adopters, he said, are most likely to be designers of microprocessors, not ASICs.

"Simplex's position is that this should sweep the whole market, but I think initially it's targeted to the high-end custom guys,"
Smith said. "It's advanced enough technology that it makes people nervous. Whenever you get something really different, it takes a
while before designers will get into it. They'll have to see some silicon come out first."

But that doesn't mean it's not a significant step. The X Architecture "should be able to take processors to the next level," he
said.

It's highly unusual for an EDA company to propose a new chip architecture. But Simplex's move may be the start of a trend, Smith
said. "Basically, EDA companies have to get closer to the silicon or they won't be able to do the job."


Divine intervention?

"If you think about how God would design a chip, obviously God would use 45° angles," said Kurt Keutzer, professor of electrical
engineering and computer science at the University of California at Berkeley. "I think [the X Architecture] is a significant
advance, and I think it's the kind of thing that will ultimately change the history of chip design." Keutzer is on Simplex's
technical advisory board, but was not personally involved in the X Architecture research.

Keutzer said that a longtime prejudice against non-Manhattan geometries has kept chip manufacturers from using 45° angles for many
years. "It's one of the things we fell asleep about. We took the prejudice as truth." Now that the X Architecture has arrived, he
said, "we've all forgotten why we couldn't do it before."

In Keutzer's view, the advantage of the X Architecture lies in the Pythagorean theorem — the shortest distance between two points
is a straight line, not a right angle. On a chip, shorter distances translate into less interconnect capacitance, thus improving
performance. Moreover, Keutzer noted, a 45° angle line will eliminate a via that's otherwise needed to connect two right-angle
lines.


Tool changes needed

"The more layers of metal you have, the more a via becomes a dicey processing problem," Keutzer said. "You've got to get alignment
across all the layers you're cutting across."

Keutzer noted, however, that EDA vendors will have to make some significant changes in their tools to fully support the X
Architecture. "Almost any tool involved in physical design will have to be re-visioned to fully exploit the opportunity," he said.

Routers, clearly, will have to change to support 45° angles. "A gridded router wouldn't begin to know what to do," Keutzer said.

But that's not all. Floor planners use routing estimation, which will have to be revamped for 45° angles, Keutzer said. Similarly,
all timing-driven placement tools use routing estimation, and that too will have to change. Clock tree distribution will be
different as well. "The changes range from modifying algorithms to rethinking the problem," Keutzer said.

The approach has not been manufactured on a large scale, and the number of partners involved with Simplex and Toshiba on the
manufacturing end suggests the fabrication problems are far from trivial.

"Since the masks are made with electron-beam systems these days, there's probably no way to direct the e-beam on a 45° angle,"
said one industry observer. "You'd probably stair-step it and remove the jaggies somehow."

Theo Claasen, chief technical officer of Philips Semiconductors (Eindhoven, Netherlands), noted that his company used
diagonal-routing techniques until geometries dipped below a half-micron. "The pitfalls [facing the X Architecture] are the same as
with all diagonal structures in the past and it has to do with the complexity of the mask making," he said. "Plus, the [EDA] tools
are square routers."

While existing semiconductor and mask-making equipment can be used for X Architecture designs, Michael Sanie, director of business
development for IC design at Numerical Technologies, acknowledged that some changes would be needed to efficiently handle diagonal
interconnects.

"One thing that's required is better handling of data," Sanie said. "Chips are denser, and there's new types of data with the X
Architecture. The infrastructure today is tuned for Manhattan-type information."

Sanie declined to say whether Numerical will offer software that specifically supports the X Architecture. He said his company's
existing tools won't have a problem with diagonal interconnects.

Bob Havemann, director of R&D at equipment maker Novellus Systems Inc., said that diagonal interconnects have not been on the
research agenda recently, though in past years "they were tried on the poly layer but created a very large database for the
reticles. At that time, designing with diagonal interconnects was not practical, but maybe things have advanced since then." As a
Texas Instruments assignee to International Sematech, Havemann ran the manufacturing consortium's copper, low-k-dielectrics
integration program.

This story was reported by Anthony Cataldo, Brian Fuller, Richard Goering and David Lammers.

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