Re: [fpu] Architecture

[Jamil Khatib <jamilkhatib75@yahoo.com>]

I got a hardcopy of the IA-64 programming manual. I'll try to summarize
what instructions are implemented in HW and what in SW also there are
some information about the programming models


Usef Saiful-Ulum wrote:

> On Wed, 19 Apr 2000, Jamil Khatib wrote:
>
> > ease of porting to other CPU cores.
>
> I didn't say this ;-)
>

May be it will be esier if we consider that the FPU will get ordered
instructions and execute them and send back the results.

I have a suggestion, can we make the FPU as a memory mapped device and
the CPU needs to write the operands in the correct address that defines
the operation and reads back the result from a specific register.
What do you think is it going to delay the CPU execution?

>
> > What about the PowerPC FPU where can I find information about it?
>
> Pwerpc is under www.motorola.com/SPS/PowerPC, but ppc FPu? i'm still
> searching.
>
> >
> > Do you suggest to start defining the building block of the FPU
>
> Sure.
>
> regards,
> Usef

Jamil Khatib



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