Re: [fpu] Architecture

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Ok I am now with you on the second approach because of its simplicity and ease of
porting to other CPU cores.

What about the PowerPC FPU where can I find information about it?

Do you suggest to start defining the building block of the FPU


Usef Saiful-Ulum wrote:

> On Tue, 18 Apr 2000, Damjan Lampret wrote:
>
> > do we want a coprocessor type of FPU or a FPU that is like a functional unit
> > in the processor. In first case all insns with opcodes reserved for FP are
> > sent to the coprocessor including FP branch and alike insns. In the second
> > case all insns including FP are issued by the CPU core (either to the IU or
> > FP functional units) and the CPU core resolves structural and data hazards.
>
> Correct, I like call this FPU as coprocessor and FPU as peripheral device,
> I also prefer the second approach so CPU core responsible to recognize
> whether it is an FP insn or not. What about making powerpc fPU as a
> starting point? Its internal data representation on FP data reg is double
> real fp format, though not like many other FPU arch, it is simple and
> easy to convert to any other formats. I'm start working on that.
>
> Some modern RISC have instruction sequencer and interface of its own (I
> mean FPU as coprocessor), so that's not true if FPU as peripheral
> device is the only choice for modern RISC.
>
> rgrds,
>
> Usef


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