[ethmac] Internal DMA & Buffer Descriptors

[kempaj@yahoo.com]

Hello,

I am wondering if anyone can be of assistance in a clarification. I 
recently (just a couple weeks ago) downloaded Igor's latest revision of 
the MAC core, and am working on integrating it for use with a soft-core 
CPU (nios) as a research project.

I've managed to sucessfully tie together the core to my logic, and poke 
registers around as well. The next step was to tackle software design, 
and I am about 90% done with a low-level driver that interfaces the 
MAC core to my TCP/IP stack. The last step will, of course, be to 
implement any MII commands for the PHY, but I'm waiting for a board 
we design with a phy on it to come back from fab.

Anyways here is the problem: I understand (I think) how BDs work for 
transmission with internal DMA. I set all the control bits as I wish, set 
the length, and set a pointer to the address in data memory where my 
TCP/IP stack has assembled a packet to send (Wishbone DMA inside of 
Igor's core masters this memory along with my CPU). I give the GO 
command and the frame is transmitted - this is all clear to me.

What is not clear to me is BD operation when receiving frames. In the 
Ethernet IP Core Specification PDF document, page 29 (frame reception) 
states: "The Ethernet IP Core reads the Rx BD...After the whole frame 
has been received and stored to the memory, the receive status and 
the pointer to memory storing the data are written to the BD".

Herein lies my confusion: How does the MAC core and/or DMA know 
where to store the received data???? I thought that the memory 
allocation for the MAC core was only for control registers and buffer 
descriptors, so this would imply that the DMA portion of the MAC 
core "knows" where to store incoming frames into memory... ideally I'd 
like to control the DMA destination from my CPU - i.e. - write a pointer 
of my choice to the Rx BD's frame pointer, and have DMA store the 
frame memory starting at that address whenever a frame comes in. 

This way, my software architecture can very easily be designed to scale 
the number of buffer descriptors in use, and statically allocate 1,500 
bytes (per ethernet packet) of memory for each descriptor.

If anyone can clarify the above operation of the Rx BDs, I would be very 
greatful!

Thank you,

Jesse Kempa
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