RE: [ethmac] 4p84: [ethmac] RE: [ethmac] 4p84: RE: [ethmac] mii rx hold time

["Illan Glasner" <iglasner@zumanetworks.com>]

Hi,
 
       Most FPGA can handle 0 hold time and Asic just the same can
handle 0 BUT if you are using a Phy you should check the Phy data sheet
for hold requirment as sometime from some few reason (usualy this mean
logic on the input or difficult rounting) the Asic have higher hold time
than 0.
 
have a nice day
 
   Illan

-----Original Message-----
From: zou.yixin@zte.com.cn [mailto:zou.yixin@zte.com.cn]
Sent: Thursday, December 27, 2001 4:37 AM
To: ethmac@opencores.org
Subject: [ethmac] 4p84: [ethmac] RE: [ethmac] 4p84: RE: [ethmac] mii rx
hold time



Hi,Igor 
I am not building my own phy.I just wonder that why they (mac and phy)
treat the output signals differently? 
The former outputs signals on the rising edge ,the latter output signals
on the falling edge?Both of 
them,howerve, sample the input signals on the rising edge. 
It is said hold time is not so important.10ns is too much,2ns is ok ? 
I have little experience in ic. I am not familiar with them ,so I  ask u
and others. 
I have learned a lot from the IP core(I am a newbie) and received a lot
of help from u and others.Thanks for all. 

Regards. 
 yxzhou 





	"Igor Mohor" <igorm@opencores.org> 
发件人： owner-ethmac@opencores.org 


2001-12-27 18:21 
请答复 给 ethmac 


        
        收件人：        <ethmac@opencores.org> 
        抄送：         
        主题：        [ethmac] RE: [ethmac] 答复: RE: [ethmac] mii rx
hold time


I would say yes. Are you building your own phy. Why do you ask that? 
  
Regards, 
    Igor 
  
  
 -----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
Behalf Of zou.yixin@zte.com.cn
Sent: 25. december 2001 12:50
To: ethmac@opencores.org
Subject: [ethmac] 答复: RE: [ethmac] mii rx hold time


In some devices(phy),signals are outputed on the falling edge of the
reference clock to meet the 10 ns 
setup and hold time. Is that necessary? 
In this core,signals(txd,txen) are outputed on the rising edge of
tx_clk. 
Both ways are ok? 
Regards. 
 & nbsp;   yxzhou 



	"Igor Mohor" <igorm@opencores.org> 
发件人： owner-ethmac@opencores.org 


2001-12-24 18:01 
请答复 给 ethmac 

        
 &nb sp;     收件人：        <ethmac@opencores.org> 
       抄送：         
       主题：        RE: [ethmac] mii rx hold time



No, tx_clk and rx_clk are not synchronous. PHY generates both signals.
Yes, the hold time will meet. tx_clk and rx_clk 
are 25 Mhz (40 ns). 
 
Regards, 
   Igor 
 
 
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@ope ncores.org]On
Behalf Of zou.yixin@zte.com.cn
Sent: 24. december 2001 9:38
To: ethmac@opencores.org
Subject: [ethmac] mii rx hold time


hi, 
Merry Christmas! 

The following  is quoted from 802.3-2000E. 
"Figure 22–15 shows the timing relationship for the signals associated
with the receive data path at the MII 
connector. The timing is referenced to the rising edge of the RX_C LK.
The input setup time shall be a minimum 
of 10 ns and the input hold time shall be a minimum of 10 ns." 

"Figure 22–14 shows the timing relationship for the signals associated
with the transmit data path at the MII 
connector. The clock to output delay shall be a minimum of 0 ns and a
maximum of 25 ns." 

When i send data synchronouly with respect to TX_CLK rising edge,can the
10ns hold time met ?I assume the tx_clk and rx_clk are
synchronous(right?). How t o avoid the hold time violation. 

Thanks. 

                          yxzhou. 




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