Re: [ethmac] lost source files

[Billditt@aol.com]

Chun-Lin,
              I am helping Igor, he is out on vacation.
Therefore, I will take a stab at answering these
questions. I am assuming you are using modelsim,
adjust accordingly for other simulators.

    glbl.v doesnt appear to be needed. For now,
I have commented  out reference to it in tb_eth_top.v
 (reference to glbl.GSR). Additionally, comment line of
code in top_modelsim.do (two lines).

       these 2 files represent vendor ram models. One is
Xilinx model, the other an artisan. Since they are copyrighted,
they cant be placed in the repository. You should download an
equivalent model from whatever vendor you are using and substitute
accordingly. In meantime, you can simulate behaviourly with the
generic_tpram.
       
ethernet/sim/rtl_sim/src/RAMB4_S16_S16.v
ethernet/sim/rtl_sim/src/art_hsdp_256x40.v

  I have a model for this, I just havent checked it in yet.
      ethernet/rtl/verilog/generic_tpram.v

       ditt
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