RE: [ethmac] wishbone dma bug

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

In ModelSIM 5.4 go to Options -> Compile -> Verilog and set "Add include
directory" to point to
the rtl directory where the files are.

Regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Hendra Gunawan
> Sent: 07. avgust 2001 9:28
> To: Igor Mohor (uni-mb)
> Cc: ethmac@opencores.org
> Subject: RE: [ethmac] wishbone dma bug
>
>
>
>
>
> > Hi,
> >
> > You didn't say much what happened. Perhaps you forgot to set the include
> > directory in
> > the ModelSim. Tell me more what seems to be the problem (error messages,
> > e
> what do you mean with include director ModelSim, is
> that work library? the other modules are ok. only the wishbone.
> thank  youe
>
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