RE: [ethmac] question : ethernet mac : PHY

["Illan Glasner" <iglasner@zumanetworks.com>]

10-May-01

   Hi,

	I belive there are few people who ask this question and since no
one answer it I would assume that there is no such code availabe or
there is such but who ever know about it keep it for himself.

in any case I belive the following "idea" will be an excpeted
replacment.

have a module with 2 ASYNC-FIFO

side A                                              Side B
txenA, txdA[3:0], txclk ---------->FIFO-1-----------> rxdvB, rxdB[3:0],
rxclk
rxdvA, rxdA[3:0], rxclk <----------FIFO-2<----------- txenB, txdB[3:0],
txclk
colA,crsA,rxerrA        <----                 ------> colB,crsB,rxerrB
                   

each side connet to your MAC so you will need to instantiate your MAC
twice.

also have two small clock generator that generate clock with different
PPM base on seed number you can change in every test.

and lastly have two async signal the col and crs for each side and by
asych I mean the 
while crs=txen|rxdv before raising the signal randomize a delay between
0 and one period time (40n in 100M)
similar to col which will have & instaed of | and again randomize
number.

txerr you most likely hocked to 0 in your MAC so it is of no intrest and
rxerr you can just give it a low percentage in random number to occur.

the point that the PHY figure out the err base on symbol etc is not
"importent" as you don't verify the PHY but rather you MAC.

the above I belive should be simple to write and will test your MAC
adequatly.

the point I prefare two MAC is that you can use one MAC and add verifier
on what the FIFO get but this mean writing almost complete MAC again as
you will want to check CRC and length etc etc and so why not simple put
another MAC.

the PHY basicly is a FIFO "that's all".

once this work you can intreduce error like if yu make the FIFO smaller
than eventually you will start see crc and small packet error, or change
the FIFO clock and you can get too long and too short easily, and so on.

have a nice day

   Illan

-----Original Message-----
From: Steve Cole [mailto:strange@lanset.com]
Sent: Thursday, May 10, 2001 11:20 AM
To: ethmac@opencores.org
Subject: [ethmac] question : ethernet mac : PHY


Im a senior college student doing a senior project with a Eth MAC 10/100
and was wondering if you know where i could get a Ethernet PHY model -
either in vhdl or verilog?  Any information / suggestions would be
greatly appreciated
steve cole