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[ethmac] Verilog - TxEthMAC

To: ethmac@opencores.org
Subject: [ethmac] Verilog - TxEthMAC
From: Novan Hartadi <novan@vlsi.itb.ac.id>
Date: Fri, 1 Dec 2000 17:49:17 +0700 (JAVT)
Reply-To: ethmac@opencores.org
Sender: owner-ethmac@opencores.org


Hi all,

Please take a look at my TxEthMAC. SO far, I don't see any errors.
I use ModelSim PE/Plus 4.7h for functional simulation.
I'm waiting your comments and suggestions.

Best regards,

- novan hartadi -

verilog_txethmac.zip

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