Re: [ecc] The soft decision decoding and else ...

[mohamed.kilani_ecc@m4x.org]

Hi everyone,

I am happy to see that you (Zalfany) are back on this mailing list ...

I worked a little bit on your code making it compilable using the Free tool 
IcarusVerilog. That needed just some syntax changes but no 
architectural ones ...

BTW, I will try to write a scope explaining the Soft Decoding Approach 
so we can work together on creating an architecture for this decoding 
method 

If you can go ahead and pipeline your design and try to synthesize it (if 
you have the tools to do that, IcarusVerilog can do that ..). There is a 
WLAN design project that needs a throughput of 54Mbps so we have a 
lot of work to do !!!!
I already changed your code to handle the used polynomial for this 
standard. The design compiles but some bugs are still there and I didn't 
have time to fix them yet, perhaps this WE ...

You are saying that you don't know what to do now ...
Don't worry if you wanna be busy, I'll keep you so :))

We can start by this soft decision thing and then we can implement APP 
decoding method (better than Viterbi) and then implement a turbo-code 
encoder/decoder ultimately and even an LDPC encoder/decoder if 
someone needs any of these ... 

I hope we will have volonteers to help out with all these nice ideas :-)

Dali, arabic/french/english speaking africain fellow living in sunnyvale, 
California ...

----- Original Message ----- 
From: "Zalfany Urfianto" <zalfany@y... > 
To: ecc@o...  
Date: Thu, 8 Nov 2001 23:24:53 +0100 
Subject: [ecc] The soft decision decoding and else ... 

> 
> 
> Hi everyone, 
> (glad to see some one start to make a discussion again on this 
> maillist :-)) 
> 
> Regarding the code that I wrote, it's been more than 10 months 
> since 
> the last time I modify the code. That's because I don't know where 
> to 
> go :-). 
> 
> I simulate the code using ModelSim, and they work fine for me. The 
> code, as far as I know, is fully synthesizable -- except for the 
> RAM 
> part [I never dare to try to synthesize them :-)]. I have a 
> colleague 
> who try to implement the code on Xilinx-FPGA, but because now I 
> live 
> far away from him I don't know his progress. I'll try to contact 
> him 
> and report the progress on this maillist. 
> 
> For the VDK9R12, the decoding process was done by hard decision 
> decoding. That's because I am not fully understand how to implement 
> a 
> soft decision decoding on Viterbi Decoder. But I think difference 
> was 
> on the branch metric calculation and the add, compare and select 
> process ? Isn't it ? If Mr Dali would like to implement the soft 
> decision decoding algorithm, great news then. Tell me what kind of 
> help that I could do. 
> 
> About the speed issue. Hmm.. this is pretty hard, mostly because I 
> believe most of high speed viterbi decoder is not constructed by 
> HDL 
> (?). As to achieve high speed, there were some kind of specific 
> hardware architecture to implement sophisticated algorithm. 
> 
> But for VDK9R12 code, the speed was very slow mainly because there 
> were only 4 unit of ACS inside, that means it would take 256/4=64 
> cycles to complete the calculation of 1 inputs. Of course then, to 
> improve the speed, why don't you try to use more ACS ? 
> 
> Another easier way to achieve speed improvement is by pipelining 
> the 
> blocks. As because when I start writing the code I was still so 
> naive 
> ^_^, all the modules works on the same cycle. Suppose you put a 
> register between them I think you could achieve a significant speed 
> improvement. 
> 
> And the last thing I want to say is, right now I am not the expert 
> at 
> the field of error correcting codes. I just found that Viterbi 
> algorithm was interesting, so I just try to code them in HDL. I use 
> the simplest algorithm and architecture that I could understand, 
> and 
> voila .. it works :-). If there were someone here who has more 
> competence on this thing and would like to share it with all of us, 
> I'm more than willing to learn from you. 
> 
> Regards to everyone, 
> - Zalfany 
>   IMIT-KTH, Kista, Sweden 
> 
> _________________________________________________________ 
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