[ecc] clock management for Reed-Solomon systems

["AJ Sahagun" <aj@asti.dost.gov.ph>]

Hi!

I don't know if this has been adressed before... but is anyone familiar or
has had experience with clock management for Reed-Solomon error correction
systems? (or ECC systems with two clocks, for that matter...)

Currently, our group is designing a (255,223) RS system with serial input
and output.  So two clocks are required, one for the input and one for the
output, with a ratio of 255/223.  These two clocks have to be synchronized,
such that, after 255 cycles of the faster clock, the slower clock will have
undergone exactly 223 cycles.

The biggest issue we see is that of "drifting" clocks, which will happen if
the clock frequency ratio is not exactly 255/223, or when either or both of
the clocks are exceptionally unstable.  When this happens, the encoding and
decoding modules might not do their job properly.

I hope someone familiar with this and related issues can help me with
this... Thanks!

---

Also, does anyone know if there are any recommended framing and symbol/bit
synchronization techniques for serial Reed-Solomon systems?  Thanks again...


_______________________________________________
"Alcohol and Calculus don't mix.  Never drink and derive."

Engr. Jonathan A. Sahagun
Science Research Specialist
Advanced Science & Technology Institute
CP Garcia Ave., UP Diliman Technopark
Quezon City, Philippines
(+632) 435-1064 (Microelectronics Division)
(+632) 435-1052 (Fax)
http://www.asti.dost.gov.ph

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