[ecc] Re:

[Chuck Sommer <ChuckSommer@mediaone.net>]

The question:
   "What should i do to ensure that
    DATA is synchronal with CLOCK?"

The answer:
    "Analysis of the timing"

The first question is what is wrong with your
solution?  To answer this some system analysis
needs to be performed at the timing of the
data and clock signals.  Also the system behavior
when SEL is changed needs to be understood.

A safe solution would be to latch DATA1 with CLOCK1
and DATA2 with CLOCK2 (into a D latch) before
performing the select/mux of DATA & CLOCK.
And if the clock delay could be tolerated , add
an additional latch after the MUX stage.

However what I have added does not fix the problem,
it only improves it.  Only timing analysis will
determine what is required.

The question is how well synchronized is
(DATA1 to CLOCK1) and (DATA2 to CLOCK2),
and what timing error is added by the
difference in delay through the MUX functions
(that is the different delay between
data .vs. clock) as this could add timing
skew.

The other issue that needs to be looked at
is how is the signal SEL changed and what
happens to the system when SEL is modified?
Does the system go into an "unknown" state
after SEL is modified and then becomes
stable again after a few clock cycles?



So the circuit would look like this:

             +-------+
             |       |
    DATA1 ---| D   Q |--- DATA1_LATCHED
             |       |
             |       |
    CLOCK1 --| CLK   |
             |       |
             +-------+

             +-------+
             |       |
    DATA2 ---| D   Q |--- DATA2_LATCHED
             |       |
             |       |
    CLOCK2 --| CLK   |
             |       |
             +-------+


                                   |\
                  CLOCK1 ----------| \
                                   |  |-- CLOCK
                  CLOCK2 ----------| /
                                   |/|
                                     | SEL

                                   |\
          DATA1_LATCHED  ----------| \
                                   |  |-- DATA
          DATA2_LATCHED  ----------| /
                                   |/|
                                     | SEL


             +-------+
             |       |
    DATA ----| D   Q |--- DATA_LATCHED
             |       |
             |       |
    CLOCK ---| CLK   |
             |       |
             +-------+



zhu.xiangyang@mail.zte.com.cn wrote:

> Hi every:
>   I want to make a circuit that can make a choice among several input
> signals, as show
> in figure gived.
>
>                                    |\
>                   CLOCK1 ----------| \
>                                    |  |-- CLOCK
>                   CLOCK2 ----------| /
>                                    |/|
>                                      | SEL
>
>                                    |\
>                   DATA1  ----------| \
>                                    |  |-- DATA
>                   DATA2  ----------| /
>                                    |/|
>                                      | SEL
>
> Here DATA1 is synchronal with CLOCK1 and DATA2 with CLOCk2.
>
>
>              +-------+
>              |       |
>     DATA1 ---| D   Q |--- DATA1_LATCHED
>              |       |
>              |       |
>     CLOCK1 --| CLK   |
>              |       |
>              +-------+
>
>
>
> (Say sorry for previous error message)
>
> --
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