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[cvs-checkins] can/ ench/verilog/can_testbench.v ench/verilog ...
CVSROOT: /home/oc/cvs
Module name: can
Changes by: mohor 02/12/26 23:12:53
Modified files:
bench/verilog : can_testbench.v can_testbench_defines.v
timescale.v
rtl/verilog : can_bsp.v can_btl.v can_defines.v
can_register.v can_register_asyn.v
can_register_asyn_syn.v can_register_syn.v
can_registers.v can_top.v
Log message:
Header changed, testbench improved to send a frame (crc still missing).
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