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[cvs-checkins] pci/ ench/verilog/pci_testbench_defines.v tl/v ...



CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/10/14 11:23:32

Modified files:
	bench/verilog  : pci_testbench_defines.v 
	rtl/verilog    : pciw_fifo_control.v 

Log message:
	Changed empty status generation in pciw_fifo_control.v

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