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[cvs-checkins] pci/rtl/verilog wb_master.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/rtl/verilog wb_master.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Fri, 11 Oct 2002 13:15:32 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/10/11 13:15:32

Modified files:
	rtl/verilog    : wb_master.v 

Log message:
	Cleaned up non-blocking assignments in combinatinal logic statements

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