[cvs-checkins] pci/rtl/verilog pci_target32_interface.v bus_c ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/08/22 12:28:23

Modified files:
	rtl/verilog    : pci_target32_interface.v bus_commands.v 

Log message:
	Updated for synthesis purposes. Gate level simulation was failing in some configurations
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