[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] ethernet/rtl/verilog eth_miim.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_miim.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 14 Aug 2002 17:32:11 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/08/14 17:32:11

Modified files:
	rtl/verilog    : eth_miim.v 

Log message:
	- Busy signal was not set on time when scan status operation was performed
	and clock was divided with more than 2.
	- Nvalid remains valid two more clocks (was previously cleared too soon).
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] ethernet/rtl/verilog eth_registers.v
Next by Date: [cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_wishbone.v
Prev by thread: [cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_wishbone.v
Next by thread: [cvs-checkins] ethernet/rtl/verilog eth_registers.v
Index(es):
- Date
- Thread