[cvs-checkins] uart16550/rtl/verilog uart_regs.v uart_receive ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/12/20 14:25:46

Modified files:
	rtl/verilog    : uart_regs.v uart_receiver.v uart_fifo.v 

Log message:
	rx push changed to be only one cycle wide.

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