[cvs-checkins] uart16550/ ench/verilog/uart_test.v oc/UART_sp ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/12/03 22:44:30

Modified files:
	bench/verilog  : uart_test.v 
	doc            : UART_spec.pdf 
	doc/src        : UART_spec.doc 
	rtl/verilog    : uart_defines.v uart_receiver.v uart_regs.v 
	                 uart_top.v uart_transmitter.v uart_wb.v 
	sim/rtl_sim/bin: sim.tcl 
Added files:
	bench/verilog  : wb_mast.v 

Log message:
	Updated specification documentation.
	Added full 32-bit data bus interface, now as default.
	Address is 5-bit wide in 32-bit data bus mode.
	Added wb_sel_i input to the core. It's used in the 32-bit mode.
	Added debug interface with two 32-bit read-only registers in 32-bit mode.
	Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
	My small test bench is modified to work with 32-bit mode.

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