[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] or1k/or1ksim sim.cfg toplevel.c cpu/common/par ...



CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	markom	01/11/14 12:33:53

Modified files:
	or1ksim        : sim.cfg toplevel.c 
	or1ksim/cpu/common: parse.c stats.c 
	or1ksim/cpu/or16: execute.c 
	or1ksim/cpu/or1k: except.c 
	or1ksim/cpu/or32: execute.c or32.c 
	or1ksim/mmu    : dmmu.c immu.c 
	or1ksim/peripheral: 16450.c 16450.h mc.c 
	or1ksim/support: simprintf.c 
	or1ksim/testbench: Makefile.am Makefile.in basic.s cfg.S 
	                   except.S except.ld excpt.S 
Added files:
	or1ksim/testbench: acv_uart.c acv_uart.cfg 

Log message:
	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml