CVSROOT: /home/oc/cvs Module name: ata Changes by: rherveille 01/07/03 15:53:03 Modified files: verilog/ocidec-1: ata.v controller.v Log message: Rewrote some sections. Minor Verilog coding style issues. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml