[oc] Registers - Multi clock domains

[yakgna narayanan <yakgnaa@yahoo.com>]

hi,
I am having one technical doubt, can anyone clear this
My doubt is :

 how to handle register for multi clock domains ?
 say for e.g
 rega      - 8 bit register
 write clk - clk1
 read clk  - clk2
 For data transfer means we can go for Asynchronous
fifo, whereas for
 registers, individual bit setting and clearing is
done in different 
clocks,
 so we cant go for RAM's also. So please guide me how
to do
 verilog code for registers in multi clock domains.

 Thanks in Advance,
 Regards,
 Yakgna


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