Re: [oc] Clock frequency generator

["Jim Dempsey" <tapedisk@ameritech.net>]

I would assume that counter is initialized to 0
or at least something between 0 and 79.
Also, since the high time and the low time are the same
why not use something like

...
// initialize somewhere
counter := 0;
sqwave_out :=0;
...
// block to flip sqwave_out on every 40 ticks
counter := counter + 1;
if counter = 40 then
sqwave_out := '1' - sqwave_out;    // XOR would be better, or use NOT
counter := 0;
end if

---------
Note, I don't know what your number base is (radix).
If octal or hexidecimal then use the bit position of the 40 as the
sqwave_out.
This would eliminate the if block.

----- Original Message -----
From: <cool_canguy@indiatimes.com>
To: <cores@opencores.org>
Sent: Monday, June 30, 2003 4:17 PM
Subject: [oc] Clock frequency generator


> hello,
>
> i am looking to match the system clock with a square wave in VHDL. so
> in my code for SQ wave...if I am generating wave as below
>
> counter := counter + 1;
>
> if counter = 40 then
> sqwave_out <= '1';
> end if;
>
> if counter = 80 then
> sqwave_out <= '0';
> counter := 0;
> end if;
>
> where sqwave_out is the sq. wave then how can I match the system
> clk with this wave. ie compare both...can someone demonstrate this to
> me in VHDL code?
>
> many thanks,
> Victor
> --
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