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Re: [oc] test_bench

To: cores@opencores.org
Subject: Re: [oc] test_bench
From: John Sheahan <jrsheahan@optushome.com.au>
Date: Tue, 29 Apr 2003 21:02:12 +1000
In-Reply-To: <200304291140.h3TBefb3002110@www.opencores.org>
References: <200304291140.h3TBefb3002110@www.opencores.org>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org
User-Agent: Mutt/1.4.1i

On Tue, Apr 29, 2003 at 10:40:41AM -0100, leire.rubio@alumni.eps.mondragon.edu wrote:
> Hello, I would like to know more about test_benches. What are they for? 

the test bench is the structure used to exercise and hence verify 
the design.

> Are they only for simulation or can be used for verification? 

simulation. 
verification is a more general area, simulation is one way.

> Are they 
> placed into the FPGA?

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References:
- [oc] test_bench
  - From: leire.rubio@alumni.eps.mondragon.edu

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