RE: [oc] UART16550 core

["Ho, Wen Jei x4297" <who1@rockwellcollins.com>]

I manually translated the Verilog UART code from OpenCore to VHDL.
It is running well in simulation. I was planning to send it back to the
OpenCore society after tested in the Lab in the near future.

If you want, I can send it to you now. However, I can't send test bench.

Wen

		-----Original Message-----
		From: owner-cores@opencores.org@ROCKWELLCOLLINS On Behalf Of
khchang@haco.co.kr
		Sent: Thursday, April 24, 2003 4:32 AM
		To: cores@opencores.org
		Subject: Re: [oc] UART16550 core



		----- Original Message -----
		From: ddresdner@p...
		To: carl@o... , cores@o...
		Date: Mon, 30 Sep 2002 23:33:16 -0100
		Subject: Re: [oc] UART16550 core

		>
		>
		> Igor,
		>
		> I would very much like to get a copy of your VHDL version
of the
		> 16550
		> Uart. We would like to use it in a project that we are
working on.
		> Would
		> it be possible to get the source for that. I would
appreciated it.
		>
		> Thank you,
		> Danny Dresdner
		>
		> ddresdner@p...
		>
		> ----- Original Message -----
		> From: "Carl van Schaik" <carl@o... >
		> To: <cores@o... >
		> Date: Tue, 7 Aug 2001 08:04:19 +0200
		> Subject: Re: [oc] UART16550 core
		>
		> >
		> >
		> > Hi Igor,
		> >
		> > > so if I understand correctly, there are two versions,
one
		> in
		> > Verilog that
		> > > was downloaded
		> > > from the opencores and one in VHDL that you wrote
		> (perhaps
		> > opencores files
		> > > translated to
		> > > VHDL and than changed).
		> > This is correct except that the Verilog was not simply
		> converted to
		> > VHDL.
		> > I have written UART's before and used the Verilog code
mainly
		> as an
		> > example
		> > for my own code for the 16550.
		> >
		> > > I don't know which ones to take for testing. I'm a
		> verilog
		> > guy, not VHDL,
		> > > although I would
		> > > take the VHDL files if they contain less bugs than the
		> ones in
		> > verilog.
		> >
		> > Well, from what I saw, the Verilog version has a few
bugs. The
		> main
		> > ones I
		> > noticed are:
		> >
		> > FIFO - not cleared when data is popped out(empty). -
Error
		> bits
		> > could remain
		> > Break detection looked a bit weird (but I'm not a
Verilog
		> person)
		> > Stop_bits signal in LCR(Line control register) is not
used.
		> > Only 16550 mode is supported, not 16540.
		> > Break error is not passed through the FIFO!
		> > Reciever will continue to recieve (0's) after a break is
		> detected.
		> >
		> > > Can you tell me if I'm correct about the differences.
		> > >
		> > > In the meantime I'll start with the Verilog files.
		> > >
		> > > Regards,
		> > > Igor
		> >
		> > regards
		> > Carl
		> >
		>
		--
		To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml

application/ms-tnef