Re: [oc] async/sync reset.

[Rudolf Usselmann <rudi@asics.ws>]

On Fri, 2003-04-11 at 01:06, cyrano@nerim.net wrote:
...
> 
> One things is bizard : sync reset could make meta stability, because you
> can't say that the release or the setting of the reset will not happen at

If that happens you did not do your job ! No, seriously
this is wrong thinking. Here is another way to look at
it: Synchronous reset requires for the reset to be
synchronous to the clock and is properly buffered through
out your chip to make sure it arrives everywhere at the
same time. If you have an external reset input, you have
to synchronize it to meet all conditions of your synchronous
reset. This is all a plan of an overall architecture. The
fact that sync reset can be properly timed and distributed
through out the system makes it such a nice thing.

> edge of the clock. In case of async reset, i can't imagine than a metastability
> could arrive at release because all state are stable waiting for the next
> clock edge (between reset and release of reset, no signal change, so no
> glitch appear when the clock egde arrive).

Wrong again. When releasing the async reset, you are faced
with two problems: 1) Releasing the reset exactly (+/- some
tolerance) at a clock edge and the data input being at the
opposite level than the reset pin. The output of the flop
will be undetermined for the first clock cycle. 2) releasing
the async reset withing the Tcq time of a flop, can violate
the setup/hold time of a following flop and cause metastability
in the next stage. Oh, and there is a third reason as well: most
tools can not time async reset correctly and it might appear at
different time (different clock cycles) through out a chip (e.g.
right side might see async reset at time n, left side at time
n+1. This will really screw your things up).

As I said before there are times for both - I prefer sync reset,
makes my job a lot easier ...

> Nicolas Boulay

Regards,
rudi
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