RE: [oc] CAN core in VHDL

["Igor Mohor\(opencores\)" <igorm@opencores.org>]

CAN is already finished in both Verilog and VHDL.
Check opencores website.

Regards,
	Igor

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org] On
> Behalf Of Emmanuel Touloupis
> Sent: Thursday, March 27, 2003 1:07 PM
> To: cores@opencores.org
> Subject: Re: [oc] CAN core in VHDL
> 
> Hi,
> 
> This isn't exactly relevant to the subject, but it is about CAN.
> 
> I want to make a CAN node and I'm looking for a board. Does anyone
know
> any
> board (Altera based preferably) that includes CAN tranciever and D-sub
> connector? Note that I want my CAN core to be implemented inside the
FPGA,
> so a board with external CAN support won't do.
> 
> Board "gurus", I would appreciate any help or alternative suggestion!
> 
> CheerS,
> 
> Manos
> 
> 
> ----- Original Message -----
> From: "Soban Shoeb Chawre" <sobanc@nital.stpp.soft.net>
> To: <cores@opencores.org>
> Sent: Monday, March 24, 2003 6:50 AM
> Subject: Re: [oc] CAN core in VHDL
> 
> 
> > hello,
> >
> > I am interesred in verifying the core.
> >
> > plz send the core, i have modelsim full version.
> >
> > thank you.
> > > Shehryar Shaheen wrote:
> > >
> > > Hello,
> > >          I have translated Igor Mohr's CAN Core in VHDL.
> > >
> > > But it has to be tested and verified (and debugged!). If any body
has
> > > full
> > > version of ModelSim (or any other simulator that
> > > supports mixed HDL simulation) and is interested in verifying the
core
> > > then
> > > I can send hime the core and it can be verified using the Verilog
> > > testbench
> > > with orignal Verilog core.
> > >
> > > Here a link that shows how to do mixed HDL simulations in ModelSim
> > > (It's pretty simple!)
> > > http://jason.sdsu.edu/modelsim/se_html/tutorial_html/t_mixed.html
> > >
> > > Anybody interested in doing this let me know
> > >
> > > Regards
> > >
> > > Shehryar
> > >
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> >
> 
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