Re: [oc] FPGA BOARD Considerations

[Héctor Orón Martínez <hecormar@teleco.upv.es>]

Mensaje citado por: robinluo <robinluo@cytecht.com>:

> Hi Héctor_Orón_Martínez,
>     I think you can read application notes in Altera websit,the file
> name is an116.pdf.

  Very interesting aplication note. Thanks.

> In the document,here is lots of config methods for FPGA.
>     Other side,why not use Altera Cyclone,it is more cheaper than ACEX1k
> an APEX20K,and it's config device is also cheap.FYI.

  I don't use Cyclone, because i already have this FPGA and have to use them. :-)

  Anyways, i think i'll do direct Jtag to FPGA and leave a port connection to
try some others. 


> 	
> Any thing,pls let me know.                  
> 
> ======= 2003-03-26 21:05:00 in your mail£º=======
> 
> >Hello,
> >
> >  I have been designing a FPGA TRAINER schematic/board for OPENCORES.
> >  Here is one problem i have find, and is memory EPROM or EEPROM for my
> 
> >devices, i'm using ACEX1K and APEX20KE. When i bought that they didn't
> send me 
> >the memory, and i asked for price, they told me i could buy from them a
> EEPROM 
> >memory with JTAG support by 20 dollars/euro (exchange is more or less
> alike), i 
> >thought to myself it is expensive, and i ask in some places, and give
> me some 
> >ideas... i could be using a DSP with memory and implement JTAG support,
> or use 
> >a microcontroller with a i2c memory (there are PIC for less than
> 10$/€), or 
> >Flash memory,...
> >
> >   As the board is intented to try out designs in a modular way, i mean
> it'll 
> >be a core and i/we'll develop some modules to hook up to the board and
> use it. 
> >For example, if someone got Burched board could hook both boards and
> could have 
> >a multiFPGA board, and try to develop a "multi-system" or to begin,
> there will 
> >be a module with and LCD, another with a 7 segment, another with IDE
> Compact 
> >Flash,...(kind like Burched).. that's what i was thinking of.
> >
> >   Taking in considerance that is a TRAINER BOARD, what would you
> recommend me 
> >for your experience to do with memory to program SRAM FPGA ? and what
> do you 
> >think of it being modular and having for that a maximum frec penalty?
> >
> >
> >
> >-- 
> >Cheers,
> > Héctor Orón                             
> mailto:hecormar@teleco.upv.es
> >--
> >To unsubscribe from cores mailing list please visit
> http://www.opencores.org/mailinglists.shtml
> >
> >.
> 
> = = = = = = = = = = = = = = = = = = = =
> 	
	
> 
> Robin Luo
> 
>        2003-03-27
> 
> 
> 
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-- 
Saludos,
 Héctor Orón                              mailto:hecormar@teleco.upv.es
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