[oc] CAN core in VHDL

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

Hello,

         I have translated Igor Mohr's CAN Core in VHDL.

 

But it has to be tested and verified (and debugged!). If any body has full

version of ModelSim (or any other simulator that

supports mixed HDL simulation) and is interested in verifying the core then

I can send hime the core and it can be verified using the Verilog testbench

with orignal Verilog core.

 

Here a link that shows how to do mixed HDL simulations in ModelSim (It's pretty simple!)

http://jason.sdsu.edu/modelsim/se_html/tutorial_html/t_mixed.html

 

Anybody interested in doing this let me know

 

Regards

 

Shehryar