|
Hi, guys and girls. I have finished the CAN core in Verilog. It is available
here: http://www.opencores.org/projects/can/ There is a small test bench which is not finished, yet. Feel
free to write (continue) works on the test bench. I’m currently adding some additional registers to the
CAN core (for status, IRQ, etc.). However the core can already be tested in HW. Feel free to contact me for more information. Best regards, Igor |