RE: [oc] Verilog

[Illan Glasner <IGlasner@mrv.com>]

Hi,

 

   ~ come before & and & come before | , with the exception of ( ) , therefore

 

A <= ((B & C) | (D & E & ((~F) | (F & G)) & (~H)));

 

also keep in mind that a || ~a && b is like a || b

 

have a nice day

 

   Illan

-----Original Message-----
From: Ho, Wen Jei x4297 [mailto:who1@rockwellcollins.com]
Sent: Monday, February 10, 2003 9:22 AM
To: OpenCores (cores@opencores.org)
Subject: [oc] Verilog

Somebody in OpenCore wrote something like:

A <= B & C | D & E & (~F | F & G) & ~H;

Could Verilog guru put in "(" and ")" for me?

 

Thanks, Wen