Re: [oc] VHDL to Verilog

[sandyns_260@eudoramail.com]

Hi,
I tried installing the demo version of Xtec Verilog <-> VHDL converter.
(downloaded from the site http://www.x-tekcorp.com/products.htm)
But when i tried to run it, it gives an error saying "XTEC_HOME should be 
set". Does anyone know how to solve this?

Regards, Sandy.
----- Original Message ----- 
From: "Ajit" <ajit@c... > 
To: <cores@o... > 
<rudi@i... > 
Date: Wed, 12 Jul 2000 09:34:09 +0530 
Subject: Re: [oc] VHDL to Verilog 

> 
> 
> 
> I prefer to convert by myself ( because I didn't get the tool when 
> wanted 
> :-) 
> You have to take care of some thumb rules in verilog 
> code-conversions 
> related to blocking/Non-blocking  assignments , putting proper 
> begin-end for 
> nested if-else -if loops etc etc and it is that easy. 
> For any verilog errors you can check it with verilint tool and for 
> checking 
> whether the code conversion is proper or not you can use high end 
> tool like 
> Formality from synopsys. 
> 
> And thats all , you are done 
> 
> 
> Best of luck 
> 
> --Ajit Madhekar 
> ControlNet India Pvt Ltd. 
> Goa, India 
> www.controlnetindia.com 
> 
> 
> ----- Original Message ----- 
> From: Rudolf Usselmann <rudi@i... > 
> To: <cores@o... > 
> Sent: Tuesday, July 11, 2000 12:25 AM 
> Subject: Re: [oc] VHDL to Verilog 
> 
> 
> > 
> > Thanks for the pointer Ajit. 
> > 
> > I downloaded the demo, and tried it. It does not seem to run 
> > for me, reports some sort of error ... 
> > 
> > Anyone had more luck ? 
> > 
> > Thanks, 
> > rudi 
> > 
> > 
> > 
> > > I remember I have seen one on 
> > > 
> > > http://www.x-tekcorp.com/products.htm 
> > > 
> > > VHDL to Verilog and Verilog to VHDL converter. 
> > > 
> > > But never used. 
> > > Give a try 
> > > 
> > > 
> > > --Ajit Madhekar 
> 
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