Re: [oc] Regarding the low power bus encoding research ?

[nico <nicolas.boulay@ifrance.com>]

On Sat, 30 Nov 2002 10:03:38 +1100
John Sheahan <jrsheahan@optushome.com.au> wrote:

> On Fri, Nov 29, 2002 at 09:14:14PM +0100, nico wrote:
> > Before regarding switching activity, you must think about clock
> > gating of the register use for the bus. Clock tree are 70% of the
> > power consumption of a chip. 
> 
> 70% is too high for the clock tree. 30% perhaps.
> Are you including the flipflop clock related power in the clock 
> tree numbers?
> 

Yes.

> > 
> > If you think of register configuration each little
> > flip-flop receive the clock, you could have hundred of them. But
> > such registers only need the clock in writing. And configuration
> > write are very uncommon. So write signal should be used to
> > mask/unmask the clock of such register bank.
> > 
> > Maybe an other way could be investigate : enable the clock of the
> > module the time to process a bus request. When playing with the
> > clock, you could have some chicken&eggs problem. It's easy to shut
> > up the clock, but impossible to reneable it without external help.
> > 
> > Maybe the bus could provide a clock enable signal. And a system
> > could let run the clock 16 or more cycles after this signal goes low
> > (the slave IP are wake up by external access but shut it-self down).
> 
> 
> clever clock gating does help power a lot. Its hard to do well. It
> makes static timing harder. 
> 

The problem is also at the transfert between 2 clocks domains, because
there is a jitter on the clock. Synthesis script must be written with
care.

> Regarding dta busses
> minimizing toggling will help power, particularly if implemented with
> clock gates.  but you have to know the data patterns to minimize the
> toggling of course. Which is pretty design specific.
> 
> for example a gray coded counter makes just over half as many edge
> transitions as a binary counter, but (I suspect) the same number if
> the address distribution is random.

Maybe there is something to gain if the buses did not toggle when the
bus as no meaning.

nicO

> john
> 
> 
> > 
> > nicO
> > 
> > On Wed, 27 Nov 2002 09:24:14 +0800
> > NansonHuang@itri.org.tw wrote:
> > 
> > > 
> > >  Hi,
> > > 
> > >  I am now surveying the papers how to achieve the on-chip low
> > >  power bus.
> > > Most of them are focus on decorrelating/encoding the bus data to
> > > reduce the switching activity. There are a lot of work on it.
> > > However, I am not sure if there are any
> > > commerical on-chip bus standard SoC product(Wishbone, AMBA,
> > > Sonic.etc) utilizing
> > > the low power encoding scheme. In others words, does it work to
> > > lower the power consumption in SoC ? Coud anyone give me some
> > > ideas to let me know if I will go on further ?
> > > 
> > >  All the best,
> > > 
> > >  Nanson
> > > 
> > > 
> > > 
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