[oc] How to generate a random std_logic_vector for simulation in VHDL

[boliu@dacafe.com]

Hi, everyone:
I have a problem of how to generate a a  random std_logic_vector in
VHDL just for simulation.
usually, I only use verilog, it sames very easy to get random in
Verilog just use a funtion from verilog.
Is there any easy way to get a random std_logic_vector in VHDL, like
use function inside the
ieee library!

Thanks all of you very much!
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