Re: [oc] VHDL uart(9600,8,N,1) help. urgent

[John Sheahan <jrsheahan@optushome.com.au>]

On Wed, Oct 02, 2002 at 08:34:49AM +0200, Igor Mohor wrote:
> You should divide your clock to 11.05MHz/(16 * 9600) = 72
> 
> You forgot to divide by 16.
> 
> Regards,
> 	Igor

only if a uart is used that uses 16 x overclocking.
sounds like no uart on transmit, which is ok. 

do you use a rs232 level translator? if so, do you have the start bit
at logic  0  , and the stop bit high on the fpga output?

and you are sending the data LSB first of course?

The receive part of the uart function benefits from oversampling to find the
centre of the bit cell, and noise.

john




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