RE: [oc] Power Calculations in ASIC

["Illan Glasner" <iglasner@zumanetworks.com>]

RRK Hi,

        For general estimation tho' it depend on verius of thing and you should get the "factors" from the vendor you work with, but for general feeling you can use :

for logic gate:

0.33uW/Gate/MHz (3.3V)

for memories and again it depend but to start with :

The current consumption ranges from 0.09mA/MHz to 0.5mA/MHz .

have a nice day

   Illan


-----Original Message-----
From: RRK [mailto:i_am_rrk@rediffmail.com]
Sent: Wednesday, July 03, 2002 10:02 AM
To: cores@opencores.org
Subject: [oc] Power Calculations in ASIC


Hi All,

Thank you for the help you all gave me regarding the SDF 
simulations-- I have been able to set up the environment for the 
same.

Now I have a new problem on hand-- I have the complete RTL in 
verilog for a complex design. (I can get the ASIC-targetted 
Netlist if I want). I am required to calculate the total power 
consumed by the design when aparticular Test_Vector is applied. 
Can any one of you PLEASE help me either by directing me to some 
text(or link on the web) which explains this or by giving me some 
of the required info yourself. I expect that if my question is not 
complete in any respect, that aspect may be informed to me so that 
I can clear myself.

Also, is it possible to get a tool which does this power 
calculation for me? if so, please direct me to it.

I thank all of you in advance and will be waiting eagerly for the 
replies.

RRK

R Ramakrishna
Associate Engineer
PortalPlayer Pvt. Ltd.
Hyderabad, India


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