Re: [oc] I2C slave model

[vikasakalwadi@rediffmail.com]

Hey, thanks for the response. But if the slave address is 4A, for that
matter any address whose msb is '0', the slave module will not
respond. It will not produce any acknowledgement. One more bug is
that, sda and scl should initially be 'x' and then pulled up to 'H',
then only the module will respond.
Can you please go through your module and let me know if the slave
works for address say 4A. Thanking you in advance,
regards,
Vikas Akalwadi
e-mail: vikasakalwadi@rediffmail.com


----- Original Message ----- 
From: Richard Herveille <richard@a... > 
To: cores@o...  
Date: Thu, 14 Mar 2002 06:06:49 +0100 
Subject: Re: [oc] I2C slave model 

> 
> 
> 
> >hi, 
> >i had developed a simple i2c bus master in VHDL and was using 
> I2C 
> >slave verilog code taht was available over here for the purpose 
> of 
> >testing. When i am giving the start, and the address of the 
> slave, the 
> >slave is not generating the acknowledgement bit. Since i donot 
> know 
> >verilog, i couldnot figureout why such problem came up. 
> >Shouldn't the slave send an acknowledgement bit after the 
> master 
> >addresses it ? 
> 
> Yes it should. 
> 
> >  If yes, can anybody let me know it the verilog slave 
> >code available over here would respond with the acknowledement 
> bit or 
> >not ? 
> 
> And yes it does. The testbench for the i2c_master_core tests this 
> bit. 
> 
> Richard 
> 
> 
> >Also let me know if there is slave module for simualtion in 
> VHDL 
> >anywhere on the web. 
> >Thanking you all in advance 
> >regards, 
> >Vikas 
> > 
> 
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