[oc] Problem with EDF format

["R. Ramakrishna" <rayaprolu_rk@yahoo.com>]

Hi everyone,

   I am Ramakrishna, from INDIA. 
   I use Xilinx Tool for Synthesis (XST or ISE 3.1i).
   We are basically working on fairly large design, in which we have a set of memories, which we
generally replace by EDN files, and then link it to the main design separately during the place
and route.  This worked sucessufully!

   Now the real deal is , we would like to do the same with a design, i.e., we would like to
synthesize a small part of design and link it to the main design similarly, but we were not able
to do so.
  Can any one please suggest if the above procedure is possible, if so, please guide me.
  Our purpose of doing it is to place two parts of the design closer to each other in FPGA so as
to 
remove glitches, which we have been encountering. Hope I am clear.

  -Thankyou.
  -Ramakrishna

__________________________________________________
Do You Yahoo!?
Send FREE Valentine eCards with Yahoo! Greetings!
http://greetings.yahoo.com
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml