RE: [oc] LVDS core

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Title:

Yair,

 

I thought LVDS was one of the interface circuits supported by FPGAs. For example to quote from Xilinix.com

about their FPGAs

 

Differential I/O standards supported include: LVDS, BLVDS, LVPECL
Other standards supported on each I/O: PCI, GTL, GTL+, AGP 2X, HSTL-I, HSTL-III, HSTL-IV, SSTL3-I, SSTL3-II, SSTL2-I, SSTL2-II, CTT, LVTTL, LVCMOS

Paul

-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On Behalf Of Yair Amitay
Sent: 13 January 2002 13:59
Cc: cores@opencores.org
Subject: Re: [oc] LVDS core

Hi,

I agree, it is a circuit design. Your attached doc describes it well.
So it is not relevant for opencores.

Thanks,
Yair.


rudi@opencores.org wrote:

200201131342.OAA17584@iza.mr2.si type="cite">

You are looking for someone to design a low-voltage
differential signaling IP core ? LVDS consists or a
transmitter and/or receiver, which one are you looking
for ?

I honestly doubt that this can be done in rtl, this is a
circuit design task. The receiver is usually an Op-Amp
type of a device, the transmitter a balanced differential
driver. 

Here is a app note from Xilinx that gives a very nice
intro to LVDS:
http://www.xilinx.com/xapp/xapp230.pdf

Cheers !
rudi


----- Original Message ----- 
From: Yair Amitay <yaira@f... > 
To: cores@o...  
Date: Sun, 13 Jan 2002 15:01:03 +0200 
Subject: [oc] LVDS core 

Hi, 

Does anybody interested to write a LVDS core ? 
I know an ASIC company that is looking for this IP. 
If yes, pls, let me know so I will contact between you and this 
company. 

Thanks, 
Yair. 

-- 

------------------------------------------------ 
Yair Amitay 
Flextronics Semiconductor 
Lod, Israel 
Phone : +972-8-9275531 
Fax : +972-8-9275552 
------------------------------------------------ 

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