Re: [oc] Re: How to create such signal wave using VHDL?

["Marko Mlinar" <markom@opencores.org>]

> Marko,
>
> find a opencore for Ethernet, implement it and then use the TCPsocket
implementation
> off a copy of Linux and translate the C into Verilog (or VHDL if you are
brave).
> Not bad for 10seconds of thinking egh? Anything I missed?

Don't want to argue - but of course:
- first you have to use Igor's Ethernet, which shouldn't be a problem
- you have to make wishbone interface in VERILOG
- supposingly your C to Verilog tool works (if you have 10k$ to buy it) you
still
have to:
- obtain TCP/IP stack from e.g. Linux
- change the behaviour of TCP/IP from SW behaviour to more like HW one,
which is IMHO
  not an easy task and change programming interface. I suppose you don't
have malloc
  or files supported with translator.
- obtain (= buy) sythesis software
- meet timing constraints, maybe not so simple
- buy a couple of big FPGAs to fit the whole design, because the Verilog to
C translator yields
  big code...

IMHO this is at least 2my of hard work...

Marko


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