RE: [oc] Re: How to create such signal wave using VHDL?

[Ramakrishna Rayaprolu <rayaprolu_rk@yahoo.com>]

hi all!!
i have been observing the interesting conversations
going on thru these mails. and i feel happy tht i am a
part of it.

i am a fresher from OU, Hyderabad, India. i have a
background in verilog coding of a few simple cores
like a fifo controller, implementation of booths alg,
a simple microcontroller(reasonably simplified, o'coz)
now that i'm in my final sem, i am required to
complete a decent project. can any one help me with an
interesting core to code in verilog? i am inclined to
code some networking protocol which might give my
career a good start. but i am ready to take up any
thing which is good enough to stand as a graduate
project. 

i request all of u to help me out.

Thank you.

Ramakrishna

__________________________________________________
Do You Yahoo!?
Check out Yahoo! Shopping and Yahoo! Auctions for all of
your unique holiday gifts! Buy at http://shopping.yahoo.com
or bid at http://auctions.yahoo.com
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml