RE: [oc] C++ to HDLs? Thats fine for breakfast now give me a challenge for lunchtime

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

> The problem with generating EDIF is that when I add two numbers together, you will have to output a low level description 
> of an adder.  Not impossible or even hard, but its been done before to a fair level of optimisation for different 
> architectures by the synthesis vendors, and may be work you don;t want to replicate (yet....)

EDIF is on list of possibilities once the basic translator is fully finished as is full C++ implementation.
 
> Couple of further questions...
> Are you going to allow floating point to be synthesised?  

Yep, not sure how yet. Is there floating point functions in Verilog?
I have only looked at basic integer bit operations so far but would
like the program to be as comprehensive as possible. If Verilog doesn't
support them then will look at way of doing it myself.

> What about pointers and ram blocks?

Pointers and ram blocks are implemented in Handel-C and possibly also the CLevelDesign 
product so I don't see any reason why I shouldn't be able to do the same. I'll also include 
support for 'external' RAMs like SSRAMs, SDRAMs and FPM DRAMs.

> function pointers?

As in "pointers to functions?", I suppose we could do something but I don't expect it to be 
perfectly transparent. Suppose we could have an array of 'phantom' memory locations for the
functions to reside at, then when they try to call the function they are pointing to, the
Verilog can do a case statement on them to see which one they want? Okay you can have
function pointers then. ;-)

> Keep up the good work!
> Cheers,
> Martin

Ta, Paul
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